1. Field of the Invention
The present invention relates to Electro-Static Discharge (ESD) protection, i.e. using mechanism, device, circuit, apparatus, or any means to protection an integrated circuit from ESD damages.
2. Description of the Related Art
Human bodies may carry a lot of electrostatic charges. When an integrated circuit is touched by a human bodies during handling, a very high voltage (˜5 KV) and a high current (˜2 A) may be generated that can damage a delicate integrated circuit. The high voltage generated may breakdown MOS gate oxides, and the high power generated by high current may damage the metallurgical junctions. To protect an integrated circuit from ESD damages, the high voltage must be clamped, the high current must be limited, and the high heat generated from the high power consumption must be quickly dissipated to protect against temperature damage.
ESD protection becomes more important in today's semiconductor industry for several reasons. Firstly, as gate oxide of the MOS devices becomes thinner, it becomes more vulnerable to ESD damages due to aggressive scaling. Secondly, the threshold voltage of MOS devices in the core logic is lower from 0.7V to about 0.4V, and the breakdown voltage is lower from 5-7V to about 3-4V that can easily escape from the junction diodes' protection. Thirdly, high speed and high frequency circuits in an integrated circuit require very small input capacitance and yet good ESD protection. However, good ESD protection often requires large silicon area and high input capacitance. Therefore, the ESD protection issues deserve revisiting in today's nanometer devices.
FIG. 1 shows a prior art ESD protection device 10 that has an I/O pad 13 protected by two junction diodes 12 and 11. The P terminal of the diode 12 is coupled to VSS and the N terminal is coupled to the I/O pad 13. Similarly, the P terminal of the diode 11 is coupled to the I/O pad 13 and the N terminal is coupled to the VDD. The junction diodes 12 and 11 have a turn-on voltage of about 0.7V and a breakdown voltage of about 5V, for example. When a high positive voltage is applied to the I/O pad 13, the I/O pad 13 can be clamped to VDD+0.7 if the diode 11 is turned on and can be clamped to 5V, if the diode 12 is broken down. Similarly, when a high negative voltage is applied to the I/O pad 13, the I/O pad can be clamped to −0.7V if the diode 12 is turned on and can be clamped to VDD-5V if the diode 11 is broken down. Thus, the high voltage of ˜3 KV can be clamped to a very low voltage. The high heat generated by the high current during diode turn-on or breakdown can be quickly dissipated by guard rings surrounding the P terminal or N terminal of the diodes. The area of the diodes tends to be very large for better ESD immunity, but the large area is relatively costly.
FIG. 2 shows a conventional ESD protection device 20 for CMOS technologies that has an I/O pad 23 protected by two MOS devices connected as diodes 22 and 21. The P terminal of the diode 22 is coupled to VSS and the N terminal is coupled to the I/O pad 23. Similarly, the P terminal of the diode 21 is coupled to the I/O pad 23 and the N terminal is coupled to the VDD. The MOS diodes 22 and 21 have a turn-on voltage of about 0.6-0.7V and a breakdown voltage of about 4-5V depending on the MOS technologies. When a high positive voltage is applied to the I/O pad 23, the I/O pad 23 can be clamped to VDD+0.7, if the diode 21 is turned on and can be clamped to 5V if the diode 22 is broken down. Similarly, when a high negative voltage is applied to the I/O pad 23, the I/O pad can be clamped to −0.7V if the diode 22 is turned on and can be clamped to VDD-5V if the diode 21 is broken down. Thus, the high voltage of ˜3 KV can be clamped to a very low voltage. Other than the MOS connected as diodes to protect integrated circuits, the junction diodes in source/drain of the MOS devices 21 and 22 can also serve for protection. In other embodiments, the ESD protection can be based on source/drain of the MOS 21 and 22 while the gates of the MOS 21 and 22 are configured as output drivers.
A diode can be fabricated from polysilicon. FIG. 3(a) shows a cross section of a polysilicon diode. To form a polysilicon diode, a polysilicon is implanted by N+ at one end and P+ at the other end with a spacing Lc in between that has intrinsic doping level. The intrinsic doping level only means not intentionally doped with any dopants but can be slightly N type or P type due to out diffusion or contamination. A silicide block layer is applied to block silicide formation on the surface of the polysilicon to thus prevent a short circuit. The two ends of P+ and N+ in polysilicon are further brought out as P and N terminals of a diode through contacts, vias, or metals. As an example of a polysilicon diode, see Ming-Dou Ker et al., “Ultra High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes with Polysilicon Diodes,” IEEE Transaction of Circuit and System-II, Vol. 54, No. 1, January 2007, pp. 47-51.
FIG. 3(b) shows current verses voltage characteristics of a polysilicon diode, such as shown in FIG. 3(a). The current verses voltage curves show useful diode behavior such as a threshold voltage of about 0.6V and a leakage current of less than 1 nA. By varying the spacing Lc, the breakdown voltage and leakage current of the polysilicon diode can be adjusted accordingly.
Polysilicon diodes can be used for ESD protection, refer to Ming-Dou Ker et al, “High-Current Characterization of Polysilicon Diode for Electrostatic Discharge Protection in Sub-Quarter-Micron Complementary Metal Oxide Semiconductor Technology,” Jpn. J. Appl. Phys. Vol. 42, 2003, pp. 3377-3378. Polysilicon structures for ESD protection in the prior arts are about a one-piece rectangular structure, which has rooms for improvements. Thus, there is still a need to use an optimized polysilicon diode structure to achieve higher ESD voltage, lower input capacitance, smaller area, and lower heat generated in today's giga-Hertz circuits.